Member Variables¶

C¶

• variable timestamps<max_count, fence>::count Number of checkpoints currently stored in dur / msg .

D¶

• variable timestamps<max_count, fence>::dur Per-checkpoint elapsed cycle counts (overhead-subtracted), indexed by record order.

E¶

• variable cpu_features::exmax Highest supported extended CPUID leaf (leaf 0x80000000 EAX).

F¶

• variable stopwatch::frequency Tick frequency of the underlying clock, captured at construction.

H¶

• variable cpu_features::has3DNOW AMD 3DNow! instructions.
• variable cpu_features::has3DNOWEXT AMD 3DNow! extension instructions.
• variable cpu_features::hasABM AMD Advanced Bit Manipulation (LZCNT + POPCNT on AMD).
• variable cpu_features::hasADX ADX instruction set (arbitrary-precision add with carry).
• variable cpu_features::hasAES AES instruction set.
• variable cpu_features::hasAVX AVX instruction set (CPUID-reported, see hasAVXOSSUPPORT).
• variable cpu_features::hasAVX2 AVX2 instruction set.
• variable cpu_features::hasAVX512BW AVX-512 Byte and Word.
• variable cpu_features::hasAVX512CD AVX-512 Conflict Detection.
• variable cpu_features::hasAVX512DQ AVX-512 Doubleword and Quadword.
• variable cpu_features::hasAVX512ER AVX-512 Exponential and Reciprocal instructions.
• variable cpu_features::hasAVX512F AVX-512 Foundation.
• variable cpu_features::hasAVX512OSSUPPORT AVX-512 state enabled by the OS (XCR0[7:5] == 0b111).
• variable cpu_features::hasAVX512PF AVX-512 Prefetch.
• variable cpu_features::hasAVX512VL AVX-512 Vector Length extensions.
• variable cpu_features::hasAVXOSSUPPORT AVX state enabled by the OS (XCR0[2:1] == 0b11).
• variable cpu_features::hasBMI1 Bit Manipulation Instructions 1.
• variable cpu_features::hasBMI2 Bit Manipulation Instructions 2.
• variable cpu_features::hasCLFSH CLFLUSH instruction.
• variable cpu_features::hasCMOV CMOVcc conditional move.
• variable cpu_features::hasCMPXCHG16B CMPXCHG16B (128-bit compare-exchange).
• variable cpu_features::hasCX8 CMPXCHG8B (64-bit compare-exchange).
• variable cpu_features::hasERMS Enhanced REP MOVSB/STOSB.
• variable cpu_features::hasF16C F16C half-precision conversion.
• variable cpu_features::hasFMA Fused Multiply-Add (FMA3).
• variable cpu_features::hasFSGSBASE RDFSBASE/WRFSBASE instructions.
• variable cpu_features::hasFXSR FXSAVE/FXRSTOR.
• variable cpu_features::hasHLE Hardware Lock Elision (Intel only).
• variable cpu_features::hasINVPCID INVPCID instruction.
• variable cpu_features::hasLAHF LAHF/SAHF in 64-bit mode.
• variable cpu_features::hasLZCNT LZCNT instruction (Intel only).
• variable cpu_features::hasMMX MMX.
• variable cpu_features::hasMMXEXT AMD MMX extensions.
• variable cpu_features::hasMONITOR MONITOR/MWAIT.
• variable cpu_features::hasMOVBE MOVBE (move byte-swap).
• variable cpu_features::hasMSR Model-Specific Registers (RDMSR/WRMSR).
• variable cpu_features::hasOSXSAVE OS enables XSAVE/XRSTOR (CPUID.1:ECX[27]).
• variable cpu_features::hasPCLMULQDQ PCLMULQDQ carry-less multiplication.
• variable cpu_features::hasPOPCNT POPCNT instruction.
• variable cpu_features::hasPREFETCHWT1 PREFETCHWT1 (Intel Xeon Phi).
• variable cpu_features::hasRDRAND RDRAND random number.
• variable cpu_features::hasRDSEED RDSEED random seed.
• variable cpu_features::hasRDTSCP RDTSCP instruction (Intel only).
• variable cpu_features::hasRTM Restricted Transactional Memory (Intel only).
• variable cpu_features::hasSEP SYSENTER/SYSEXIT.
• variable cpu_features::hasSHA SHA instruction set.
• variable cpu_features::hasSSE SSE.
• variable cpu_features::hasSSE2 SSE2.
• variable cpu_features::hasSSE3 SSE3.
• variable cpu_features::hasSSE41 SSE4.1.
• variable cpu_features::hasSSE42 SSE4.2.
• variable cpu_features::hasSSE4a AMD SSE4a.
• variable cpu_features::hasSSSE3 SSSE3.
• variable cpu_features::hasSYSCALL SYSCALL/SYSRET (Intel only).
• variable cpu_features::hasTBM AMD Trailing Bit Manipulation.
• variable cpu_features::hasXOP AMD XOP.
• variable cpu_features::hasXSAVE XSAVE/XRSTOR.

I¶

• variable cpu_features::isAMD Vendor string is "AuthenticAMD".
• variable cpu_features::isIntel Vendor string is "GenuineIntel".

L¶

• variable timestamps<max_count, fence>::last Cycle count captured by init or the most recent record ; used as the reference point for the next duration measurement.

M¶

• variable cpu_features::max Highest supported standard CPUID leaf (leaf 0 EAX).
• variable cpu_features::model NUL-terminated CPUID model/brand string (leaves 0x80000002–4).
• variable timestamps<max_count, fence>::msg Per-checkpoint labels, parallel to dur .

P¶

• variable cpu_features::padding1
• variable cpu_features::padding2

R¶

• variable timestamps<max_count, fence>::rdtsc_overhead

S¶

• variable stopwatch::start_time Tick count captured at construction.

V¶

• variable cpu_features::vendor NUL-terminated CPUID vendor string (leaf 0).